The Clip Is Not the Chip: Towards Full-Chip ILT

Neural inverse lithography technology (ILT) methods are benchmarked at the scale of small standalone features, orders of magnitude below a real exposure field; whether their accuracy composes to full-chip scale is untested. We evaluate six models --- NeuralILT, DAMO, GAN-OPC, CFNO, and two training variants of Penumbra, an 8-bit-quantized U-Net for FPGA deployment --- on two $2048\times2048$\,px macro crops rasterized from a real GF180MCU shuttle: one of the densest available blocks, far outside training distribution; and one deliberately selected to be close on fill fraction, feature width, spacing, and contour density. All models run at their own native window with no resizing. GAN-OPC, despite competitive clip-level scores, collapses outright at macro scale and prints zero pixels in both cases; an earlier Penumbra variant trained on unaligned tile crops shows the identical collapse signature, traced to a periodic tiling artifact. Retraining Penumbra on fixed-grid tiles with a central-region loss removes the artifact and restores printability, achieving the lowest whole-macro $L_2$ on the dense crop and ranking third of six on the density-matched crop, at the cost of worse edge-placement error on standard LithoBench clips. Simulating the resist image across all $456$ LithoBench test cases isolates a tile-seam error that decays toward each tile's interior and is present in both Penumbra variants. The results indicate that clip-level accuracy does not directly extrapolate to larger areas, but that a positionally-tiled window is a valid mechanism for full-chip scale.