PCB Gym: Benchmarking Agentic PCB Layout

Printed circuit board (PCB) layout is the task of physically implementing an electronic circuit by placing components on a board and routing copper traces between them. Existing benchmarks evaluate LLMs on subsets of the layout task, such as routing over human-seeded placements. We present PCB Gym, an environment and benchmark for joint agentic circuit board placement and routing. While layout typically starts from a visual schematic, we provide design intent in Zener, an open-source hardware description language for schematic-as-code. Our problem data comes from open-source hardware designs, ranging in complexity from 2–12 copper layers, and we evaluate generated boards with the combination of deterministic gates and a rubric-based agentic grader. We observe that frontier LLMs produce DRC-valid and completely routed boards on 32.1% of attempts; however, they frequently make mistakes such as routing power rails like ordinary signals.