Evidence-Bound Verification for Agentic SystemVerilog Workflows

Large-language-model agents can generate RTL, assertions, testbenches, and verification plans, but their completion claims become unreliable when specifications or dependent artifacts change. We propose an evidence-bound assurance workflow for agentic SystemVerilog development. Requirements, register specifications, RTL, assertions, simulation results, synthesis checks, and human approvals are represented as versioned artifacts connected through an explicit dependency graph. Agent actions are constrained by machine-readable contracts, while completion is accepted only when independent deterministic tools produce evidence bound to the exact artifact versions evaluated. Upstream changes automatically invalidate affected evidence and approvals, preventing stale results from being reused, and selective recertification reruns only impacted checks. We specify a prespecified evaluation on a bounded RISC-V system-on-chip workflow incorporating an AXI-Lite-controlled DSP accelerator. The comparison covers human-only engineering, an unconstrained tool-using coding agent, and a governed evidence-bound workflow across controlled change events. Primary outcomes are invalidation recall and stale-evidence escapes; supporting outcomes include recertification effort, schedule variance, and human intervention. The contribution is not a claim of formally proved RTL correctness. It is a falsifiable assurance architecture and experimental protocol for maintaining machine-checkable verification evidence across iterative agent-assisted hardware development.