Trace2Repair: LLM-Assisted Repair of Processor Performance Models from Simulation Trace Analysis

The creation of timing models for processors allows fast timing estimates for architectural exploration or software profiling. Such models are either hand-written in languages such as C++ or generated from architecture description languages (ADLs), such as CorePerfDSL. Yet, it is sometimes hard and time-intensive to capture all timing characteristics of a processor pipeline from analysis of the datasheet, RTL or instruction timing traces. Such inaccuracies can be discovered by validating performance simulator traces against real hardware or cycle-accurate RTL references. However, even after a local timing discrepancy is identified, determining which modeled mechanism caused it and how the corresponding timing model should be modified still requires substantial model-specific reasoning and manual effort. Therefore, we present an LLM-assisted framework for diagnosing and repairing timing inaccuracies in performance simulators using RTL–simulator trace mismatches. Trace2Repair instruments the timing variables used by the performance simulator, aligns RTL and simulator traces using local inter-instruction timing differences, and constructs compact mismatch windows augmented with simulator and architectural evidence. Guided LLM reasoning then identifies likely timing-error causes and repair targets, which are translated into minimal modifications. We evaluate Trace2Repair on the Rocket and Ibex RISC-V cores using Embench and a performance simulator that combines an ADL-based pipeline model with C++-implemented timing models for components such as branch predictors and caches. The average relative CPI error is reduced from 13.73% to 2.11% on Rocket and from 22.90% to 0.000093% on Ibex, demonstrating that trace-level diagnosis and targeted repair can substantially improve the performance models.