Chip Protection Area Design: Dataset and Evaluation

The protection area surrounding a semiconductor chip guards its circuit against thermo-mechanical defects induced during wafer dicing. Its designs are governed by 2D manufacturing constraints and evaluated using test chips that require complex design and production processes and incur substantial costs. An ideal design should achieve optimal mechanical states while meeting constraints, creating a highly nonlinear optimization landscape where data-driven approaches could show strong promise. Given the lack of large-scale semiconductor protection area datasets with 3D thermo-mechanical elasto-plastic evaluation, we propose the first 1.17 TB public dataset, containing 110,170 protection area layouts across 18 metal stacks, each paired with fields from thermo-mechanical elasto-plastic finite element simulations. We demonstrate that the dataset enables two key benchmarks: design-to-fields cross-dimensional forward prediction, and fields-to-design inverse generation. The baselines show that data-driven approaches can become reliable solutions for industrial bottlenecks. In addition to the dataset, we provide an open-source end-to-end automated pipeline from design generation to simulation.