Hardware-Algorithm Co-Design for Hyperdimensional Computing Based on Memristive System-on-Chip

Hyperdimensional computing (HDC), with its highly efficient computing paradigm, provides a parallel and fast-learning algorithm for artificial intelligence (AI), making it well-suited for resource constrained applications like edge intelligence. In-memory computing (IMC) systems based on memristive devices complement this by offering energy-efficient hardware solutions. To harness the advantages of both memristive IMC hardware and HDC algorithms, we propose a hardware-algorithm co-design approach for implementing HDC on a memristive System-on-Chip (SoC). On the hardware side, we utilize the inherent randomness of memristive crossbar arrays for encoding and employ analog IMC for classification. At the algorithm level, we develop hardware-aware encoding techniques that map data features into hyperdimensional vectors, optimizing the classification process within the memristive SoC. Experimental results in hardware demonstrate 90.71\% accuracy in the language classification task, highlighting the potential of our approach for achieving energy-efficient AI deployments on edge devices.