The IID: A Natively Probabilistic Reconfigurable Computer

We demonstrate the IID, a natively probabilistic, reconfigurable digital computer based on stochastic digital circuits. The IID Mark 0 is implemented on top of a commodity array of Field Programmable Gate Arrays (FPGAs), and programmed using a generic toolchain based on the State-Density-Kernel abstractions from Blaise. It can be used to perform MCMC inference on factor graphs with hundreds of thousands of variables in real time. The technical novelty of the IID rests in the stochastic digital circuits which it simulates. These circuits enable the construction of massively parallel, low bit precision, fault tolerant machines that directly simulate Markov chains in hardware, leveraging small XOR-SHIFT RNGs to provide the necessary stochasticity. Due to space constraints, we refer the reader to FIXME cite for technical details about these circuits, including a detailed discussion of their capabilities and their novelty and an overview of the software tools used to program the IID to solve arbitrary discrete factor graphs. The key consequence of our approach is that the IID can be used to solve probabilistic graphical model problems with 2-3 orders of magnitude improvement in price/power/performance product and 3-6 orders of magnitude improvements in robustness to bit errors than is possible using conventional computer architectures.