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The Policy-gradient Placement and Generative Routing Neural Networks for Chip Design
Ruoyu Cheng · Xianglong Lyu · Yang Li · Junjie Ye · Jianye Hao · Junchi Yan

Wed Nov 30 09:00 AM -- 11:00 AM (PST) @ Hall J #200

Placement and routing are two critical yet time-consuming steps of chip design in modern VLSI systems. Distinct from traditional heuristic solvers, this paper on one hand proposes an RL-based model for mixed-size macro placement, which differs from existing learning-based placers that often consider the macro by coarse grid-based mask. While the standard cells are placed via gradient-based GPU acceleration. On the other hand, a one-shot conditional generative routing model, which is composed of a special-designed input-size-adapting generator and a bi-discriminator, is devised to perform one-shot routing to the pins within each net, and the order of nets to route is adaptively learned. Combining these techniques, we develop a flexible and efficient neural pipeline, which to our best knowledge, is the first joint placement and routing network without involving any traditional heuristic solver. Experimental results on chip design benchmarks showcase the effectiveness of our approach, with code that will be made publicly available.

Author Information

Ruoyu Cheng (Department of Computer Science and Engineering, Shanghai Jiao Tong University)
Xianglong Lyu (Shanghai Jiaotong University)
Yang Li (Shanghai Jiao Tong University)
Junjie Ye (The Chinese University of Hong Kong)
Jianye Hao (Tianjin University)
Junchi Yan (Shanghai Jiao Tong University)

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