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Parallel Implementations of Learning Algorithms: What have you done for me lately?
Robert Thibadeau · Dan Hammerstrom · David S Touretzky · Tom Mitchell

Sat Dec 13 07:30 AM -- 06:30 PM (PST) @ Hilton: Sutcliffe A
Event URL: http://www.cs.cmu.edu/~dst/NIPS/nips08-parallel-algorithms.html »

Interest in parallel hardware concepts, including multicore, specialized hardware, and multimachine, has recently increased as researchers have looked to scale up their concepts to large, complex models and large datasets. In this workshop, a panel of invited speakers will present results of investigations into hardware concepts for accelerating a number of different learning and simulation algorithms. Additional contributions will be presented in poster spotlights and a poster session at the end of the one-day workshop. Our intent is to provide a broad survey of the space of hardware approaches in order to capture the current state of activity in this venerable domain of study. Approaches to be covered include silicon, FPGA, and supercomputer architectures, for applications such as Bayesian network models of large and complex domains, simulations of cortex and other brain structures, and large-scale probabilistic algorithms.

Author Information

Robert Thibadeau (Seagate Technology)
Dan Hammerstrom (Portland State University)
David S Touretzky (Carnegie Mellon University)

Research Professor in the Computer Science Department and the Center for the Neural Basis of Cognition at Carnegie Mellon University, Pittsburgh PA.

Tom Mitchell (Carnegie Mellon University)

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